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00019 #ifndef INCLUDED_USRP2_IMPL_H
00020 #define INCLUDED_USRP2_IMPL_H
00021
00022 #include <usrp2/usrp2.h>
00023 #include <usrp2/data_handler.h>
00024 #include <usrp2_eth_packet.h>
00025 #include <boost/scoped_ptr.hpp>
00026 #include "control.h"
00027 #include "ring.h"
00028 #include <string>
00029
00030 #define MAX_SUBPKT_LEN 252
00031
00032 namespace usrp2 {
00033
00034 class eth_buffer;
00035 class pktfilter;
00036 class usrp2_thread;
00037 class usrp2_tune_result;
00038 class pending_reply;
00039 class ring;
00040
00041
00042 struct db_info {
00043 int dbid;
00044 double freq_min;
00045 double freq_max;
00046 double gain_min;
00047 double gain_max;
00048 double gain_step_size;
00049
00050 db_info() : dbid(-1), freq_min(0), freq_max(0),
00051 gain_min(0), gain_max(0), gain_step_size(0) {}
00052 };
00053
00054 class usrp2::impl : private data_handler
00055 {
00056 static const size_t NRIDS = 256;
00057 static const size_t NCHANS = 32;
00058
00059 eth_buffer *d_eth_buf;
00060 std::string d_interface_name;
00061 pktfilter *d_pf;
00062 std::string d_addr;
00063 usrp2_thread *d_bg_thread;
00064 volatile bool d_bg_running;
00065
00066 int d_rx_seqno;
00067 int d_tx_seqno;
00068 int d_next_rid;
00069 unsigned int d_num_rx_frames;
00070 unsigned int d_num_rx_missing;
00071 unsigned int d_num_rx_overruns;
00072 unsigned int d_num_rx_bytes;
00073
00074 unsigned int d_num_enqueued;
00075 omni_mutex d_enqueued_mutex;
00076 omni_condition d_bg_pending_cond;
00077
00078
00079 pending_reply *d_pending_replies[NRIDS];
00080
00081 std::vector<ring_sptr> d_channel_rings;
00082 omni_mutex d_channel_rings_mutex;
00083
00084 db_info d_tx_db_info;
00085 db_info d_rx_db_info;
00086
00087 int d_tx_interp;
00088 int d_rx_decim;
00089
00090 void inc_enqueued() {
00091 omni_mutex_lock l(d_enqueued_mutex);
00092 d_num_enqueued++;
00093 }
00094
00095 void dec_enqueued() {
00096 omni_mutex_lock l(d_enqueued_mutex);
00097 if (--d_num_enqueued == 0)
00098 d_bg_pending_cond.signal();
00099 }
00100
00101 static bool parse_mac_addr(const std::string &s, u2_mac_addr_t *p);
00102 void init_et_hdrs(u2_eth_packet_t *p, const std::string &dst);
00103 void init_etf_hdrs(u2_eth_packet_t *p, const std::string &dst,
00104 int word0_flags, int chan, uint32_t timestamp);
00105 void stop_bg();
00106 void init_config_rx_v2_cmd(op_config_rx_v2_cmd *cmd);
00107 void init_config_tx_v2_cmd(op_config_tx_v2_cmd *cmd);
00108 bool transmit_cmd(void *cmd, size_t len, pending_reply *p, double secs=0.0);
00109 virtual data_handler::result operator()(const void *base, size_t len);
00110 data_handler::result handle_control_packet(const void *base, size_t len);
00111 data_handler::result handle_data_packet(const void *base, size_t len);
00112 bool dboard_info();
00113 bool reset_db();
00114
00115 public:
00116 impl(const std::string &ifc, props *p, size_t rx_bufsize);
00117 ~impl();
00118
00119 void bg_loop();
00120
00121 std::string mac_addr() const { return d_addr; }
00122 std::string interface_name() const { return d_interface_name; }
00123
00124
00125
00126 bool set_rx_gain(double gain);
00127 double rx_gain_min() { return d_rx_db_info.gain_min; }
00128 double rx_gain_max() { return d_rx_db_info.gain_max; }
00129 double rx_gain_db_per_step() { return d_rx_db_info.gain_step_size; }
00130 bool set_rx_lo_offset(double frequency);
00131 bool set_rx_center_freq(double frequency, tune_result *result);
00132 double rx_freq_min() { return d_rx_db_info.freq_min; }
00133 double rx_freq_max() { return d_rx_db_info.freq_max; }
00134 bool set_rx_decim(int decimation_factor);
00135 int rx_decim() { return d_rx_decim; }
00136 bool set_rx_scale_iq(int scale_i, int scale_q);
00137 bool set_gpio_ddr(int bank, uint16_t value, uint16_t mask);
00138 bool set_gpio_sels(int bank, std::string src);
00139 bool enable_gpio_streaming(int bank, int enable);
00140 bool write_gpio(int bank, uint16_t value, uint16_t mask);
00141 bool read_gpio(int bank, uint16_t *value);
00142 bool start_rx_streaming(unsigned int channel, unsigned int items_per_frame);
00143 bool rx_samples(unsigned int channel, rx_sample_handler *handler);
00144 bool stop_rx_streaming(unsigned int channel);
00145 unsigned int rx_overruns() const { return d_num_rx_overruns; }
00146 unsigned int rx_missing() const { return d_num_rx_missing; }
00147
00148
00149
00150 bool set_tx_gain(double gain);
00151 double tx_gain_min() { return d_tx_db_info.gain_min; }
00152 double tx_gain_max() { return d_tx_db_info.gain_max; }
00153 double tx_gain_db_per_step() { return d_tx_db_info.gain_step_size; }
00154 bool set_tx_lo_offset(double frequency);
00155 bool set_tx_center_freq(double frequency, tune_result *result);
00156 double tx_freq_min() { return d_tx_db_info.freq_min; }
00157 double tx_freq_max() { return d_tx_db_info.freq_max; }
00158 bool set_tx_interp(int interpolation_factor);
00159 int tx_interp() { return d_tx_interp; }
00160 void default_tx_scale_iq(int interpolation_factor, int *scale_i, int *scale_q);
00161 bool set_tx_scale_iq(int scale_i, int scale_q);
00162
00163 bool tx_32fc(unsigned int channel,
00164 const std::complex<float> *samples,
00165 size_t nsamples,
00166 const tx_metadata *metadata);
00167
00168 bool tx_16sc(unsigned int channel,
00169 const std::complex<int16_t> *samples,
00170 size_t nsamples,
00171 const tx_metadata *metadata);
00172
00173 bool tx_raw(unsigned int channel,
00174 const uint32_t *items,
00175 size_t nitems,
00176 const tx_metadata *metadata);
00177
00178
00179
00180 bool config_mimo(int flags);
00181 bool fpga_master_clock_freq(long *freq);
00182 bool adc_rate(long *rate);
00183 bool dac_rate(long *rate);
00184 bool tx_daughterboard_id(int *dbid);
00185 bool rx_daughterboard_id(int *dbid);
00186
00187
00188
00189 bool burn_mac_addr(const std::string &new_addr);
00190 bool sync_to_pps();
00191 bool sync_every_pps(bool enable);
00192 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
00193 bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
00194 };
00195
00196 }
00197
00198 #endif